Integrated circuits typically include a number of input/output pins which are used for communication with additional circuitry. For example, an integrated memory device such as a dynamic random access memory (DRAM) includes both control inputs for receiving memory operation control signals, and data pins for bi-directional data communication with an external system or processor.
The data transmission rate of modern integrated circuits is primarily limited by internal circuitry operating speeds. That is, communication networks have been developed which can transmit signals between circuitry at a rate that is faster than the capacity of many integrated circuits. To address the need for faster circuits, a group of integrated circuits can be combined on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data which is transmitted at a high speed. For example, a group of memory devices, such as DRAMs, static RAMs, or read only memories (ROM), can be connected to a common data bus. The data rate of the bus may be substantially faster than the feasible operating speed of the individual memories. Each memory, therefore, is operated so that while one memory is processing received data, another memory is receiving new data. By providing an appropriate number of memory devices and an efficient control system, very high speed data transmissions can be achieved.
As the transmission rate of the data communication signals continues to increase, new circuitry and methods are needed to accurately receive data at each integrated circuit. One proposed solution is a bus interface described in U.S. Pat. No. 5,513,327. This bus interface uses two edge triggered receivers to latch data. The first receiver operates in response to a rising edge of a clock signal while the second receiver operates in response to the falling edge of the clock. Further, the data bus is not terminated at a midsupply level and output is transmitted on the bus using an open drain configuration.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a high speed input buffer which can operate independently, or in combination with another input buffer, to receive data in response to a transition of a bus clock.